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UID:pretalx-osfc-2026-9HUU8E@talks.osfc.io
DTSTART;TZID=CET:20260915T103000
DTEND;TZID=CET:20260915T110000
DESCRIPTION:High-speed interfaces are rare on MCUs\, and cost-effective FPG
 As often come with limited LUTs\, leaving developers caught between slow p
 rotocols like I2C/UART and the complexity of rolling a custom SPI protocol
  from scratch.\n\nThis talk explores a cleaner alternative: interfacing an
  FPGA as a memory-mapped device with an MCU running Zephyr\, and extending
  that interface to expose gateware peripherals inside the FPGA. We'll cove
 r two approaches\, direct memory mapping over STM32's FMC bus\, and a QSPI
 -based approach treating the FPGA as a SPI memory device\, comparing their
  trade offs in speed\, complexity\, and flexibility.\n\nKey takeaways:\n\n
 1) Writing Devicetree for Memory mapped FPGAs using STM32’s FMC Bus.\n2)
  Writing Devicetree for Memory Mapped FPGAs using Generic serialised SPI/Q
 SPI interfaces.\n3) Using the FPGA as MMU for external memory like HyperRA
 M.\n4) Interfacing gateware peripherals in the FPGA from MCU running Zephy
 r
DTSTAMP:20260720T183922Z
LOCATION:Main
SUMMARY:Memory-Mapped FPGA Peripherals on Zephyr: FMC and QSPI Approaches -
  Sahaj Sarup
URL:https://talks.osfc.io/osfc-2026/talk/9HUU8E/
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