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UID:pretalx-osfc-2026-PZQ8JW@talks.osfc.io
DTSTART;TZID=CET:20260916T165000
DTEND;TZID=CET:20260916T172000
DESCRIPTION:There has been a long-term urban legend around the difficulty o
 f implementing native DRAM initialization in coreboot.\nFirmware code runn
 ing at this stage has no main memory available\, and must grapple with a\n
 small amount of CPU cache as data storage.\n\nDRAM initialization entails 
 retrieving memory chip characteristics for each channel\, calculating comm
 on parameters\, programming a large set of memory controller registers\, a
 nd then DDR PHY registers.\nAfterwards a set of SoC-specific and JEDEC-sta
 ndard training algorithms must be performed to empirically derive a set of
  delays based on limited hardware-level signal feedback.\nAnd all this has
  lived in proprietary "MRC" blobs with hardly any documentation for a long
  time\,\ndeterring most coreboot developers from even attempting to produc
 e open source code for this task.\n\nThis talk takes the 10+ year-old Inte
 l Bay Trail platform\, which has lived in coreboot ever since\nChromebooks
  were released with this SoC.\nInstead of focusing on the low-level detail
 s of this specific platform\, this talk will use it as a\ncase study for m
 odern techniques for reverse engineering and then implementing open source
  code\nfor this DRAM initialization step.\n\nIt will showcase the use of S
 erialICE modernized with the Unicorn Engine to trace the operation of bina
 ry blobs\, and how it can also be repurposed and combined with new harness
 es to allow the rapid prototyping of the core algorithms. It will then sho
 w how careful\, skeptical use of modern LLM-based tooling accelerated the 
 conversion of this into a working\, prototype-quality coreboot implementat
 ion capable of booting on multiple real boards.
DTSTAMP:20260720T183543Z
LOCATION:Main
SUMMARY:Teaching an Old SoC New Tricks: Native raminit for Bay Trail - Mate
  Kukri
URL:https://talks.osfc.io/osfc-2026/talk/PZQ8JW/
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