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SUMMARY:Memory-Mapped FPGA Peripherals on Zephyr: FMC and QSPI Approaches 
 - Sahaj Sarup
DTSTART;TZID=Europe/Berlin:20260915T103000
DTEND;TZID=Europe/Berlin:20260915T110000
DTSTAMP:20260817T125502Z
UID:pretalx-osfc-2026-9HUU8E@talks.osfc.io
DESCRIPTION:High-speed interfaces are rare on MCUs\, and cost-effective FP
 GAs often come with limited LUTs\, leaving developers caught between slow 
 protocols like I2C/UART and the complexity of rolling a custom SPI protoco
 l from scratch.\n\nThis talk explores a cleaner alternative: interfacing a
 n FPGA as a memory-mapped device with an MCU running Zephyr\, and extendin
 g that interface to expose gateware peripherals inside the FPGA. We'll cov
 er two approaches\, direct memory mapping over STM32's FMC bus\, and a QSP
 I-based approach treating the FPGA as a SPI memory device\, comparing thei
 r trade offs in speed\, complexity\, and flexibility.\n\nKey takeaways:\n\
 n1) Writing Devicetree for Memory mapped FPGAs using STM32’s FMC Bus.\n2
 ) Writing Devicetree for Memory Mapped FPGAs using Generic serialised SPI/
 QSPI interfaces.\n3) Using the FPGA as MMU for external memory like HyperR
 AM.\n4) Interfacing gateware peripherals in the FPGA from MCU running Zeph
 yr
LOCATION:Main
URL:https://talks.osfc.io/osfc-2026/talk/9HUU8E/
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