Status update for AMD openSIL and Coreboot integration
10-12, 13:00–13:15 (US/Pacific), Main Track

This is a status update on current status of AMD openSIL project, openSIL code base has been upstream on public GitHub, coreboot port for 4th Generation AMD EPYC Processor should be open for review before end of July.

AMD openSIL description

AMD openSIL is re-architecture of x86 AGESA FW stack. AMD openSIL adheres to simple goals of an agnostic set of library functions written in an industry-standard language that can be statically linked to the host firmware without having to adhere to any host firmware protocols. AMD openSIL is designed to be scalable and simple to integrate, light weight, low chirp and transparent, potentially allowing for an improved security posture.

Link to AMD openSIL source code

New support added in coreboot upstream port
- Multiple root hub support added
- Resource allocator v4 (match HW setup with code and ACPI)
- amdfwtool updates
- IVRS generation for multiple root bridges
- unified handling of IOAPIC

Coreboot port upstreaming in prrogress topic:amd_genoa_opensil

Detailed information on openSIL Blog

Future plans for openSIL + coreboot

Firmware Engineer, passionate about all things firmware and open source.