10-10, 15:00–15:30 (US/Pacific), Main Track
Looking at multiple RISC-V firmware projects and processors, this talk compares how their approaches to providing a RISC-V platform align, such that operating systems and applications can be easily ported across them.
We start with a summary of recent progress on RISC-V in the coreboot project and its fork oreboot. During the development of oreboot, we noticed that while RISC-V is already an extensible ISA with many ratifications in place and the first application SoCs produced, they do not yet fully define platforms. Details such as memory access and clear protocols of what an OS may or may not be able to control and handle are still open issues, so that the same application may behave different from one piece of hardware to another.
With this talk, we dive deep into a socio-technical design discussion on strategies around unaligned memory access, how hardware may or may not support it, how it can be handled with traps in M-mode, S-mode or simply by what compilers emit, how hypervisors change perspectives, and what a full stack could look like that takes hardware, firmware, OS, compilers and application software design into account.