2025-10-08 –, Main
Intel® FSP (Firmware Support Package) is a critical component in the silicon bring-up processes, traditionally provided by Intel® as a binary to be integrated with a bootloader of customer’s choice (while source is provided for specific purposes).
As the demands of firmware development and enabling evolve, Intel recognizes the need for securing Intel assets like FSP, is more critical than ever. Intel is introducing “Signed FSP and Verified Boot Architecture” to provide integrity protection to Intel® FSP binary. This is the latest addition to the slew of capabilities that are already part of FSP, that will continue to expedite development cycles, enhance co-validation with customers, increase the velocity of deploying fixes in a secure manner and help customers launch products faster into the market.
This strategic shift involves significant architectural changes, such as simplifying bootloader – FSP interactions and implementing a robust signing and verification process through Intel's Root of Trust. These advancements not only harden silicon initialization but also enable standalone Intel® FSP updates in-field, offering a more streamlined approach to firmware development and management.
In this talk, we will explore the motivations behind Intel's Signed FSP approach and the benefits it provides to Intel’s customers. Attendees will gain insights into how these changes transform the boot flow, reduce integration efforts and help to reassign valuable engineering resources from FSP integration and validation to firmware development.
Ravi Rangarajan is a Firmware Engineer working on implementing Edge requirements on Intel platforms. Additionally, Ravi is an evangelist for enabling open source firmware solutions for IA platforms.
Rangasai (Sai) Chaganty is a firmware engineer with more than 20 years of experience working on Intel Architecture solutions with expertise in UEFI firmware architecture and Intel(R) FSP architecture. Additionally, Sai is active in various tech talks within Intel and also serves as the chair of SMBIOS Working Group within DMTF.
Chris is a Software Enabling and Optimization Engineer and a Technical Lead within the Edge Computing Group at Intel. He specializes in firmware bring-up, debugging and enabling of security technologies like Intel® BootGuard.
Chis has a 20+ years of Industry experience in BIOS, test software development and debugging. Based in Munich, Germany, Chris is supporting ECG customers in EMEA with x86 based board designs.